Memory interleaving is known in computer processing systems and applications, for distributing memory space into two or more memory banks. Such interleaving allows simultaneous and/or contiguous access of the two or more memory banks, thus avoiding read/write wait time delays that may be incurred if all memory addresses were mapped to a unified non-interleaved memory structure. Accordingly, memory interleaving can offer significant benefits in terms of memory access bandwidth and memory access speed.
With reference to FIG. 1, a simple two-way memory interleaving scheme into two memory banks is illustrated. A 32-bit address 102 (A[31:0]) may be used to address a memory (not illustrated), wherein odd addresses, for example, are directed to a first memory bank (not illustrated) through a first memory channel, channel Ch0 108_0, and all even addresses directed to a second memory bank (not illustrated) through a second memory channel, channel Ch1 108_1. In order to accomplish this, a simple channel spreading function, 104 is illustrated, where the least significant bit of address 102 (i.e., bit A[0]) can be used to decide which channel to route a particular address to. For example, if an even numbered value appears on address 102, bit A[0] would be “0,” which can be used to direct the related memory access to first memory channel Ch0 108_0 (e.g., based on the simple channel spreading function 104 comprising selection signal CS0, for enabling access to first memory channel Ch0 108_0, being set to the value ˜A[0]). Similarly, an odd numbered value of address 102, based on bit A[0] being “1” can be used to the related memory access to second memory channel Ch1 108_1 (e.g., where channel spreading function 104 further includes selection signal CS1 to be based on A[0] for selecting second memory channel Ch1 108_1). The remaining higher order bits of address 102 are used for intra-channel addressing function 106, i.e., addressing the memory space contained within each of the first and second memory banks pertaining to first and memory channels Ch0 108_0 and Ch1 108_1.
While the above simple scheme works well for two-way interleaving (or in general, interleaving for a number of memory channels equal to a power of 2), such schemes are not easily or efficiently scalable. For example, if a three-way interleaving is desired between three memory channels in a particular memory architecture, conventional memory interleaving techniques cannot accomplish a uniform interleaving across the three memory channels using a simple technique as that illustrated in FIG. 1 for two-way interleaving. This is because a similar channel spreading function for three-way interleaving may require the two lowest order bits of address 102, for example, to select between the three memory channels. However, two bits produce four binary bit combinations (i.e., “00,” “01,” “10,” and “11”), and simply remapping addresses pertaining to the additional bit combination to one of the three memory channels would lead to lack of uniformity in dividing the addresses between the three memory channels, which is undesirable.
In an attempt to overcome the above drawbacks, particularly related to three-way interleaving, a conventional approach involves the use of a wider data bus, which is wide enough to access all three memory channels at the same time. For example, a 192-bit wide data bus may cover read and write accesses for all three memory channels pertaining to a 32-bit memory space. However, such conventional approaches are wasteful and do not exploit the benefits of interleaving; they tend to be inefficient in terms of power and area. Moreover, such approaches are closely tailored for a three-way interleaving and thus, are not scalable to interleaving across other numbers of memory channels.
Yet another conventional approach for three-way interleaving utilizes a mod-3 (modulus of 3) channel spreading function along with a table look up to select between the three channels for directing addresses. However, this approach involves an inelegant use of the modulus function, which are not efficiently mapped using the mod-3 spreading function. Implementing a mod-3 function requires hardware similar to that for implementing a hardware divider, which as one skilled in the art would understand, is expensive. Accordingly, this approach is also not desirable.
Other such approaches known in the art are similarly inefficient and lack scalability, simplicity, and uniformity in spreading functions. Therefore, there is a need for spreading functions which are scalable (e.g., beyond just 3, to other number of channels, such as, 5, 7, 13, etc.); configurable in their degree of spreading (e.g., less aggressive/more aggressive); and simple, cheap, and fast with regard to their implementation.